Aegis: High-Performance Zero-Copy Packet Processing Framework

Welcome to the official documentation site for Aegis.

Aegis is a low-latency, multi-threaded Deep Packet Inspection (DPI) and packet filtering framework inspired by architectural patterns commonly used in high-performance packet processing systems, quantitative trading infrastructure, and network security software.

Technical Highlights

Zero Heap Allocation on the Hot Path: Pre-allocated contiguous memory pools (PacketBufferPool) manage packet memory. All components pass cache-aligned indices and zero-copy packet slices rather than allocating dynamic arrays or buffers.
Lock-Free Producer/Consumer Queues: Uses bounded, single-producer single-consumer (LockFreeSPSCQueue) structures aligned to 64-byte CPU cache lines (alignas(64)) to completely eliminate mutex contention and false sharing.
Zero-Copy Packet Parsing: Designed PacketView containing offsets and nested sub-views directly mapping to raw packet header bytes, avoiding string copying.
Flow Affinity: Distributes packets to dedicated worker cores using 5-tuple consistent hashing, ensuring flow affinity and enabling local connection tracking without cross-core locks.
Deterministic Latency: All critical path algorithms use bounded structures, avoiding dynamic memory expansion or locks that introduce latency spikes.
Benchmark-Driven Optimization: Optimization iterations are verified against microbenchmarks measuring nanosecond-level components.

Pipeline Architecture

Aegis stages are connected by bounded lock-free ring buffers to pipeline packet ingestion and analysis without mutex contention:

               [ Ingest / PCAP Reader ]
                           │
                 Lock-Free SPSC Queue
                           │
                   [ Load Balancer ]
                           │
             ┌─────────────┴─────────────┐
             │                           │
    Lock-Free SPSC              Lock-Free SPSC
             │                           │
      [ Worker Core 0 ]           [ Worker Core N ]
             │                           │
    Lock-Free SPSC              Lock-Free SPSC
             └─────────────┬─────────────┘
                           │
                    [ Polling Writer ]
                           │
                   [ Output PCAP / File ]

Documentation Quick Links

Getting Started

Windows Setup Guide: Compile and verify Aegis using MSVC and CMake on Windows.
DPI & Networking Tutorial: Fundamental networking concepts, header parsing details, and packet journeys.

Core Design Specifications

Architecture Design: Pipeline orchestrations, thread models, and synchronization details.
Memory Architecture: Cache-friendly contiguous pool buffer pre-allocations.
Concurrency Model: Memory barriers, lock-free ring buffers, and RCU configurations.
Rule Engine & State: RCU-based subnet/wildcard rules and local connection maps.

Performance & Metrics

Benchmark Methodology: Performance measurement details and microbenchmark profiling.
Optimization Log: Historical log of compiler, memory, and concurrency optimization phases.
Complexity Analysis: Big-O time and space complexity table for hot path operations.

Developer Reference

Architecture Decision Records (ADR): Chronological catalog of foundational engineering choices.
Coding Standards: Modern C++ style guide, error handling guidelines, and compiler warning settings.
Interview Appendix: Systems engineering interview questions and whiteboarding details.