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Performance Design & Latency Budget: Aegis Packet Engine

1. Latency Budget Allocation (Target Goals)

To achieve real-time Deep Packet Inspection, we establish target budgets for processing latency. Actual values will be measured and logged using the benchmark suite.

Target Pipeline Latency Goals:

  Step                     Target Allocation   Status / Cache State
  -----------------------  ------------------  -------------------------
  1. Buffer Acquisition    < 5% of cycle cost  L1 Cache (Local Pool)
  2. Parse Ethernet/IP/TCP  < 10% of cycle cost L1/L2 Cache (Raw Bytes)
  3. Flow Table Lookup     < 20% of cycle cost L2/L3 Cache (Prefetched)
  4. DPI (SNI Extraction)  < 40% of cycle cost L1/L2 Cache (Payload)
  5. Rule Match            < 20% of cycle cost L1/L3 Cache (Trie/Map)
  6. Queue Dispatch        < 5% of cycle cost  Lock-Free Ring Buffer
  7. Stats Update          < 2% of cycle cost  Thread-Local (No Mutex)
  -----------------------  ------------------  -------------------------
  Total Budget Goal:       To be benchmarked   (Worker Core Processing)

The latency profiles of each operation will be captured incrementally during optimization phases and compared against the baseline Packet_analyzer implementation.

2. Low-Latency Guidelines & Trade-offs

2.1 Eliminate Heap Allocations (malloc / new)

  • Problem: Standard memory allocators take locks and perform complex search routines, causing unpredictable latencies (p99 latency spikes of up to milliseconds).
  • Solution: Aegis bans new and malloc on the data path. All memory (flows, packets, queues) is pre-allocated at startup. Pools are implemented as simple array-backed structures.

2.2 Cache Locality and Prefetching

  • Flow Entries: To maximize L1/L2 cache hits, the flow entry struct is compact (under 128 bytes) and padded to 64 bytes.
  • Prefetching: During parsing, worker threads can issue software prefetch instructions (__builtin_prefetch on GCC/Clang) for the payload data that will be inspected during DPI.

2.3 CPU Cache Hierarchy References

  • L1 Cache Access: ~1 ns
  • L2 Cache Access: ~3-4 ns
  • L3 Cache Access: ~12-15 ns
  • Main Memory Access (DRAM): ~60-80 ns
  • NUMA Cross-Socket Access: ~100-150 ns

Aegis minimizes main memory accesses by keeping flow states and tables localized to each core's L3/L2 cache.

3. Measurable Metrics & Profiling Strategy

3.1 Real-Time Metrics Exporter

  • Aegis exposes atomic counters for packets processed, bytes processed, drops, and queue depths.
  • A high-resolution timer (std::chrono::high_resolution_clock) tracks latency histograms in microsecond bins.

3.2 Profiling Tools

  • Perf & Flame Graphs: Used to analyze hotspot functions on Linux. Compile with -fno-omit-frame-pointer.
  • Sanitizers: Compile with -fsanitize=address,undefined (ASan) to check correctness and -fsanitize=thread (TSan) to verify lock-free safety.
  • Valgrind Cachegrind: Used to audit cache misses and instruction counts.